RTE RBC 2oo2 Reference Application 0.1.0 build 0006685
SIL 4 2oo2 Dual-Site Fault-Tolerant ERTMS Radio Block Centre Reference Architecture
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interfaces Directory Reference

Detailed Description

ERTMS/ETCS Level 2 RBC System Interfaces

This directory contains the formal architectural and protocol specifications for the external interfaces of the Radio Block Centre (RBC) in an ERTMS/ETCS Level 2 railway signaling system.


Interface Index

Interface Document Subsystems Primary Standards & References Description
RBC <-> Train Interface RBC $\longleftrightarrow$ Train (ETCS On-Board Unit / EVC) UNISIG Subset-026 (SRS Ch. 7 & 8), Subset-039 (Euroradio FIS), Subset-040 Standard Track-to-Train and Train-to-Track radio messages (Msg 2, 3, 15, 16, 24, 33, 129, 132, 136, 146, 155, 159) and ETCS Packets (P0, P3, P5, P15, P21, P27, P41, P58, P65, P72).
RBC <-> Interlocking Interface RBC $\longleftrightarrow$ Interlocking (IXL / CBI) CENELEC EN 50128 SIL 4, EN 50159, EULYNX SCI-RBC, UNISIG Subset-098 Vital safety protocol for Route status/locking, Track Section occupancy, Signal aspects, Point/Switch detection, Level Crossings, Train Footprint confirmation, and Early Section Release.
CTC <-> RBC Interface CTC / TMS $\longleftrightarrow$ RBC UNISIG Class 1 RBC, Traffic Management System (TMS) Guidelines Traffic supervision, Train Describer & Timetable integration, Real-time Train Telemetry, Dispatcher TSR management, Emergency Stop zones, and RBC Health/Redundancy monitoring.
Note
Important Distinction: Target ERTMS Level 2 Specification vs. Current Simplified Simulation Protocol:
  • Domain Architecture & Target Specification: The documents in this directory and the C header models in src/application/AB/GP/ertms/ and src/application/AB/GA/ertms/ specify the complete, formal ERTMS Level 2 interfaces targeting full UNISIG Subset-026, EULYNX IXL, and CTC integration.
  • Current Simulator Testbed Adaptation: For initial integration and lightweight container testing, the current Python test simulators (RBC_Test_Sim_Train, RBC_Test_Sim_IL, RBC_Test_Sim_CTC) and POSIX codec (rbc_wire.c / rbc_wire.py) implement a compact simplified wire subset (defined in RBC_Test_Env/doc/design/SIM_INTERFACES.dox), which maps directly into these formal domain structures.

System Context Architecture

graph TD
    subgraph Operations & Traffic Management
        CTC["CTC / TMS (Centralised Traffic Control)"]
    end

    subgraph Wayside Signaling (SIL 4)
        IXL["Interlocking (IXL / CBI)"]
        RBC["Radio Block Centre (RBC 2oo2 SIL 4)"]
    end

    subgraph Rolling Stock (SIL 4)
        EVC["Train On-Board Unit (ETCS EVC / OBU)"]
    end

    CTC <-->|"CTC <-> RBC Protocol (Telemetry, TSR, Schedule)"| RBC
    IXL <-->|"RBC <-> IL Vital Protocol (Routes, Occupancy, Footprint)"| RBC
    RBC <-->|"Euroradio GSM-R / FRMCS (Subset-026 Msg 3, 15, 24, 136)"| EVC

Implementation Reference

The corresponding C99/C11 safety-critical header definitions (conforming to MISRA C:2012 and CENELEC EN 50128 SIL 4) are located in: